Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!
We’re building a new team to influence a product roadmap and deliver a market-leading System IP solution. With architecture scalability at the frontier of our design focus, our performance- and power optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.
Being part of a new team at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. Our growing team is made up of talented individuals with vastly diverse background and skill sets. You will always be learning while helping us shape the team’s culture.
Role and Responsibilities
As a member of our System IP team, you will be a key contributor tasked with performance analysis, RTL correlation and performance verification of future generation mobile memory system designs. You will be responsible for working on development of custom coherent interconnect IP, memory controller and last level cache blocks. In this role you will be interacting with the system architects, verification team, design implementation teams and performance/power teams.
Key Responsibilities Include:
Define/plan/implement/execute performance verification strategy of complex System IP designs.
Ability to delve into the lowest level details of Coherent fabric, Memory controller & LLC design specification, implementation and it's performance impact.
Interactions with architects and design engineers to define detailed scope of micro architectural features.
Develop tools to analyze performance data, identify bottlenecks and propose solutions to improve end-to-end performance
Engage with partners and customers to provide projections of key performance indicators on workloads of interest
Develop methodology and testbench for performance verification, analyze correlation results, and interact with RTL & modeling teams to drive fixes into the design and the model
Create scalable micro benchmarks to validate features.
Build infrastructure/tooling needed for efficient performance correlation debug.
Agility to work on multiple tasks/projects.